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CONFERENCE-AT-A-GLANCE

 

Wednesday, September 26

Registration
7:00 a.m. -
5:00 p.m.

 

Plenary Session
8:30 a.m. -
11:45 a.m.

Opening Remarks:
   Wei Hwang, General Conference Chair
Suhwan Kim, General Conference Co-Chair
Chung-Yu (Peter) Wu, President of National Chiao Tung University
Technical Program Overview:
   Thanh Tran, Technical Program Chair
Keynote Presentation:
   Dr. Jackson Hu, Chairman and CEO, United Microelectronic Corporation
Plenary Presentations:
   Mr. Dave HoltPresident and CEO, Lightspeed Logic, Inc.
Dr. Heinrich Meyr, Director, Institute for Integrated Signal Processing Systems, Aachen University of Technology

Lunch
11:45 a.m. -
1:00 p.m.

Reception Lunch
ASIC - ASIC/SOC - SOCC
20th Year Anniversary

Technical Sessions
1:00 p.m. -
2:40 p.m.

Track A
WA2:
Analog Design for SoC

Track B
WB2:
DSP and Embedded Systems

2:40 p.m. -
3:30 p.m.

CONCURRENT POSTER SESSION

3:30 p.m. -
5:10 p.m.

WA3:
RF Circuits and Systems

WB3:
Network and Reconfigurable Architectures

Thursday, September 27

Registration
7:30 a.m. -
5:00 p.m.

 

Technical Sessions
8:30 a.m. -
10:10 a.m.

Track A
TA1: Low Power Design Techniques

Track B
TB1: Industrial SoC Applications and Methods

10:30 a.m. -
11:45 a.m.

TA2: Power Management Techniques

TB2: System Level Design Methodology

Luncheon
11:45 a.m. -
1:15 p.m.

Guest speaker:
Dr. Sheng-Chun (Paul) Lo, Sr. VP and GM of Analog/Mixed-Signal   IC Design Group, Synopsys, Inc.

Technical Sessions
1:40 p.m. -
3:20 p.m

Track A
TA3: Embedded Memories

Track B
TB3: Design Tools for SoC

3:30 p.m. -
5:10 p.m.

Panel Discussion
“Why is Analog SOC Design still Black Magic?”

Friday, September 28

Registration
8:00 a.m. -
3:30 p.m.

 

Technical Sessions
8:30 a.m. -
10:10 a.m.

Track A
FA1: High Performance Digital Circuits and Systems

Track B
FB1: Design for Testability, Manufacturability and Validation

10:30 a.m. -
12:10 p.m.

FA2: Signal Integrity and In-Chip Interconnections

FB2: Wireline and Wireless Communications

Lunch
12:10 p.m. - 1:30 p.m.

Reception Lunch

 

Tutorial Track A

Tutorial Track B

1:30 p.m. -
2:20 p.m.

TFA1
System Level Design of Analogue Mixed Signal SoC
Gerhard Nössing & Karsten Einwich, Infineon Technologies

TFB1.1
Introduction to ESL design methodology
Dr. Alan Su, Springsoft Inc., Taiwan

2:20 p.m. -
3:10 p.m.

TFB1.2
Development of a virtual platform for multimedia SoC
Prof. Sao-Jie Chen, EE Department, National Taiwan University

3:10 p.m. -
3:30 p.m.

Coffee Break

3:30 p.m. -
4:20 p.m.

TFA2
Using Mask Reconfigurable Logic to reduce risk and add flexibility to Platform SOCs
Lyle Smith, Lightspeed Logic's Chief Scientist

 

TFB2.1
Code generation for SIMD ISA
Prof. Yu-Hen Hu, IECE Dept, University of Wisconsin, Madison

4:20 p.m. -
5:10 p.m..

TFB2.2
Development of an embedded OS for a SIMD processor
Prof. Pao-Ann Hsiung, CS Department, National Chung-Cheng University

Saturday, September 29

CULTURAL TOUR

CONFERENCE ENDS